Hyperscalers are designing their way around Nvidia with bespoke accelerators — but only two firms can co-design them at scale, and they all funnel through the same TSMC nodes and CoWoS slots.
Tightness
+4 this quarter — ASIC shipments now outgrowing merchant GPUs for the first time, with new programs (Apple, OpenAI, Anthropic) added — but the design duopoly and shared TSMC/CoWoS chokepoints keep it tight.
Hyperscaler accelerators — Google TPU, Amazon Trainium, Meta MTIA, Microsoft Maia — are how the largest buyers cut their Nvidia dependence. But the hyperscalers don't build them alone: Broadcom and Marvell together do ~95% of the custom-ASIC co-design work, and every one of these chips is fabricated by TSMC on advanced nodes and assembled with CoWoS. So custom silicon doesn't escape the compute bottleneck — it inherits the same foundry and packaging chokepoints as merchant GPUs.
A generational efficiency leap from Nvidia or AMD that undercuts the economics of building custom chips, or TSMC advanced-node and CoWoS capacity catching up. Neither looks likely to bite before mid-2027, which is when TSMC constraints are expected to ease.
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