The passive silicon slab that wires HBM to logic inside CoWoS is reticle-limited and eats TSMC wafer capacity — so as AI packages balloon past reticle size, usable interposers per wafer collapse and packaging can't scale faster.
Tightness gaugeCritical
Tightness
71/ 100Critical
+4 this quarter — Interposers are made by TSMC inside CoWoS and are physically capped by the lithography reticle. As package sizes scale to 5.5x reticle and beyond, a 300mm wafer yields only a handful of large interposers, and panel/glass alternatives are years from volume — keeping this acutely tight.
In CoWoS-S, the silicon interposer is the wafer-level layer that carries the dense interconnect between logic chiplets and the HBM stacked beside them. Because it is patterned by lithography it cannot exceed the reticle limit without stitching, and producing it consumes TSMC foundry capacity. As designs push past 3.3x reticle, only a few good interposers come off each round wafer — a hard cap on how many top-end accelerators can be packaged.
NearMigration to CoWoS-L (LSI bridge) and CoWoS-R (organic RDL) eases the reticle ceiling for the largest packages.
2026TSMC CoPoS panel pilot line completes (~June 2026); early glass-interposer qualification.
2027–2029CoPoS/glass mass production and possible SiC-interposer adoption on Rubin-class parts break the round-wafer area limit.
What would loosen it
Shift to LSI-bridge (CoWoS-L), organic RDL (CoWoS-R) and panel/glass (CoPoS) packaging that escapes the circular-wafer area limit — but meaningful volume relief is a 2028+ event.
Latest developments
2026-04-13
TSMC CoPoS panel-level pilot line tooling underway (completion ~June); mass production eyed 2028–2029 as Rubin's 5.5x reticle yields as few as 4 units per wafer.