Panel-level packaging entrants matter to the AI buildout because the dominant advanced-packaging format, TSMC's CoWoS, anchors AI accelerators to a round silicon interposer that is both expensive and constrained in area. A cohort of companies is now racing to replace that interposer with glass panels, potentially breaking the bottleneck that, as of late 2025, was dictating lead times for chips like Nvidia's Blackwell and Rubin series more than raw silicon supply.
The core technology shift is from circular wafer-level processing to large rectangular panels carrying a glass core. Glass offers lower coefficient of thermal expansion, better dimensional stability, and compatibility with co-packaged optics, properties that organic substrates cannot match at the package sizes AI accelerators now require. Through-glass vias enable dense vertical interconnects, and the flat panel geometry allows more dies and HBM stacks per substrate than a silicon interposer permits.
The leading entrant is Absolics, an SKC affiliate backed by Applied Materials, which built a facility in Covington, Georgia, with an annual stated capacity of 12,000 square meters of glass panels, enough to supply substrates for an estimated two to three million chip packages the size of Nvidia's H100. In May 2025, Absolics received a $40 million initial installment under the U.S. CHIPS Act, and by mid-2025 it was in pre-qualification discussions with AMD and Amazon Web Services. Mass production was targeted for late 2025 to 2026.
Powertech Technology, the world's leading memory packaging and testing provider, entered as a direct CoWoS alternative with its PiFO (Pillar Integration FO) platform, a square panel-level format using a glass substrate. Industry sources cited its production cost as roughly 30 percent lower than CoWoS-L, and by late 2025 most of Powertech's advanced packaging capacity for 2026 had already been committed. The company announced a record capital expenditure target of NT$40 billion for 2026, double its prior-year level.
Samsung Electro-Mechanics launched a pilot line at its Sejong facility in 2025 and in November of that year established a joint venture with Sumitomo Chemical to secure upstream glass core materials, targeting glass substrate products for high-end SiP applications in 2026. Separately, JNTC established a South Korean facility capable of producing 10,000 semi-finished glass panels per month in 2025. TSMC itself unveiled its CoPoS (Chip-on-Panel-on-Substrate) roadmap using glass as an interposer, with a pilot line at VisEra planned for 2026 and mass production targeted between 2028 and 2029.
The chokepoint risk is a yield race. Pilot lines are operational, but scaling glass panel processes to volume production involves warpage management, fragility during fabrication, and entirely new supply chains for high-purity glass, challenges analogous to the industry's earlier 200mm-to-300mm wafer transition. For now, panel-level packaging entrants hold a Watch designation: the strategic direction is clear, but commercial volumes remain limited and qualification cycles with hyperscaler customers are still in early stages.